Dans le cadre du Labex CominLab, un séminaire sur le thème de l'intégration 3D et les communications optiques intégrées aura lieu le vendredi 9 novembre à partir de 9h30 en salle Sardaigne de l'Irisa

 

Veuillez trouver ci-dessous le programme du séminaire.

 
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9h30
Titre : Réseaux photoniques dans les architectures 3D
Sébastien Le Beux : Maitre de conférences, Ecole Centrale de Lyon 
Institut des Nanotechnologies de Lyon

Résumé : Trends in design of the next generation of Multi-Processors System on Chip (MPSoC) point to 3D integration of thousand of processing elements, requiring high performance interconnect for high throughput and low latency communications. Optical on-chip interconnects enable significantly increased bandwidth and decreased latency. They are thus considered as one of the most promising paradigms for the design of such system. However, existence of interfaces between electronic and photonic signals implies strong constraints on the layout of the 3D architecture and may impact the architecture scalability. In this presentation, we propose and evaluate a possible layout for an optical Network-on-Chip used to interconnect processing elements located on different electrical layers.
 
 
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10h30

Titre : On-chip communication infrastructure based on photonics communication layer
Ian O'Connor, professeur des universités, Ecole Centrale de Lyon
Institut des Nanotechnologies de Lyon

Résumé : The advent of high-performance computing architectures is necessary to follow Moore's Law and allow the execution of future software applications both in terms of resolution (audio, video and scientific computing) and in terms of computing power or MIPS (real-time coding/decoding, data encryption/decryption). However, the use of conventional technologies will lead to several device-level hurdles (leakage currents, interconnect limitations, quantum effects …) It is widely recognized that conventional technology scaling will at some point break down in the face of these limits, both for fundamental and for economic reasons. Alternatives must be found, at both architectural and device levels. In this talk, I will look at the emergence of silicon photonics technologies and present research led in the Heterogeneous Systems Design group at the Lyon Institute of Nanotechnology, to assess their potential in the context of on-chip communication infrastructures in future manycore computing platforms. I will present a heterogeneous integration approach for a photonics communication layer in multicore computing architectures, as well as the expected gain in performance for both point to point links and for wavelength-routing networks on chip.
 

Contact:Daniel Chillet